Cilus
laborare est orare
Actually architecture wise AMD has always shown something new to the world. But sometimes they implemented in correctly in one go (like Athlon 64 bit), sometimes after couple of tries (Phenom to Phenom II).
Actually how the architecture is implemented is very muchimportant too. Intel is always ahead on it, their architecture might not be very innovative, but implementation is very good, every small element that are part of the architecture, performs very close to its expected performance.
Now we are seeing that AMD is losing ground in single Core performance or we can say in ILP but it is AMD who actually first implemeted separate L1 Data Cache and l1 instruction cache to reduce the coherency issues of ILP techniques like Pipelining, Superscalar etc. Initially Data and instructions are used to reside inside a single L1 cache, resulting cache coherency problem, slow access and inefficient use of cache size.
Actually how the architecture is implemented is very muchimportant too. Intel is always ahead on it, their architecture might not be very innovative, but implementation is very good, every small element that are part of the architecture, performs very close to its expected performance.
Now we are seeing that AMD is losing ground in single Core performance or we can say in ILP but it is AMD who actually first implemeted separate L1 Data Cache and l1 instruction cache to reduce the coherency issues of ILP techniques like Pipelining, Superscalar etc. Initially Data and instructions are used to reside inside a single L1 cache, resulting cache coherency problem, slow access and inefficient use of cache size.