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darklord
Cyborg Agent
FSB - It is the bus through which the CPU interacts with the memory controller that is situated in the Northbridge [chipset]. This is applicable to Intel.
FSB is not applicable to AMD A64 because the MCH or memory controller hub is located on the CPU itself. For communication with the chipset and other devices,the CPU interacts through Hypertransport Link.Its a different kind of Bus.
I hope that explains your query.
FSB is not applicable to AMD A64 because the MCH or memory controller hub is located on the CPU itself. For communication with the chipset and other devices,the CPU interacts through Hypertransport Link.Its a different kind of Bus.
I hope that explains your query.
The MCH is on die so i dont think there is any need for the CPU to interact with the MCH via HTT link
dOm1naTOr
Wise Old Owl
In case of AMD[K8 architecture], the CPU nd memory runs at same FSB. So if u overclock the FSB inorder to oc the CPu, ull be overclocking the memory also.
Suppose if u oc ur FSB from 200 to 240, then ur proccy [say a 3200+ with FSB of 200 and multiplier of 10x] wud run at 240*10= 2.4Ghz from 2.0 Ghz and ur memory wud run at (240*2)=480 Mhz, and in dual channel, it wud give u 960Mhz. So for AMF if u wanna bring a new standard of memory[maybe of higher frequency], then the entire architecture shud be changed. the FSB of CPU shud be increased.
In case of Intel, the FSB affects the CPU and the MCP only. If u wanna oc RAM, then ull have to do it seperately. Its easy to implement newer memory standards as only the MCp has to be upgraded.
But AMD's onchip mem controller does a very decent job which enables the accesing of memory directly by CPU and no need for the mobo chipset to come in between. So even a 2-3-2-5 400MHZ@ 1T memory in dual channel in AMD cud beat Intel's 667 @ 4-4-4-14 @2T in dual ch in memory benchmarks.
For nforce 4 nd 5 chipsets for AMD, there are 20 PCIE lanes of which 16 is used by the display card, and there are only 4 of them left for other activities like I/O, SATA, serial nd parralel communications. But if u use an ATI Xpress 200 based mobo, it has a total of 24 lanes. So ull have 8 lanes left for other purposes[Theoritically better than nforce architecture, but practically performs more or less same as nforce].
Suppose if u oc ur FSB from 200 to 240, then ur proccy [say a 3200+ with FSB of 200 and multiplier of 10x] wud run at 240*10= 2.4Ghz from 2.0 Ghz and ur memory wud run at (240*2)=480 Mhz, and in dual channel, it wud give u 960Mhz. So for AMF if u wanna bring a new standard of memory[maybe of higher frequency], then the entire architecture shud be changed. the FSB of CPU shud be increased.
In case of Intel, the FSB affects the CPU and the MCP only. If u wanna oc RAM, then ull have to do it seperately. Its easy to implement newer memory standards as only the MCp has to be upgraded.
But AMD's onchip mem controller does a very decent job which enables the accesing of memory directly by CPU and no need for the mobo chipset to come in between. So even a 2-3-2-5 400MHZ@ 1T memory in dual channel in AMD cud beat Intel's 667 @ 4-4-4-14 @2T in dual ch in memory benchmarks.
For nforce 4 nd 5 chipsets for AMD, there are 20 PCIE lanes of which 16 is used by the display card, and there are only 4 of them left for other activities like I/O, SATA, serial nd parralel communications. But if u use an ATI Xpress 200 based mobo, it has a total of 24 lanes. So ull have 8 lanes left for other purposes[Theoritically better than nforce architecture, but practically performs more or less same as nforce].
darklord
Cyborg Agent
Well MCP [shipset] does communicate with the CPU via HTT,i know that,just that i am saying MCH [memory controller] being on die there is no need for an external medium for communication
I guess that happens by default with any platform, i mean FSb and Memory run in Sync
What you say is perfectly correct,only if 1:1 divider is used
not otherwise.Lower dividers can be used to lower memory clocks There is absolutely no need to change the architecture.Take the case of Socket 939 n Socket AM2.AM2 is just DDR2 compatibility upgrade,the entire K8 architecture is exact same,just the MCH was changed from DDR1 to DDR2,thats all
FSB or more precisely HTT in this case cant be increased,reason being, HTT 1.0 specifies base frequency as 200MHz ,therefore 200MHz x 5 [HTT multiplier] = 1000 x 2[since its DDR] = 2000 MT/s that AMD specifies.And that hasnt changed from DDR to DDR2 transition i.e Socket 939 to AM2.What happened with AM2 is base frequency rmeained same hence AM2 CPUs are still rated to work at 1000MT/s but DDR2 base frequency started from 533,although 400 DDR2 was there.So the MCH,in the CPU detected the Memory Speed through the SPD,used the correct Divider and worked,thats it
Many who use AM2 must have observed that the memory speed used to be detected something weird with older BIOS'es,thanks to AM2 confusing memory dividers. Intel Platform also has Memory bound to FSB,it cant clock seperately.ou can use Dividers to increase or decrease Memory speed at Stock FSB but it still depends upon the FSB speed.Its recently that Nvidia's 680i SLI has allowed independant memory overclocking irrespective of the FSB speed[Although its proven,it isnt 'Truly' independant and that some weird,never seen before dividers are used.] and ATI/AMD RD600 which offered 'True' independant memory clocking.
Totally....
The on chip MCH implementation reduces latencies like anything and gives immense bandwidth efficiency.Infact ironically there is soo much bandwidth reserve in K8 CPUs,its never fully utilised. Same is the case with HTT bus and AMD is already bringing HTT 3.0 which will increase current 2000 MT/s speed to 4000 MT/s or so
Add to that a DDR2/DDR3 compatible Memory controller,just imagine the amount of bandwidth avlbl. Sheeesh !- Status