Ram Latencies are:
tCAS
The number of clock cycles needed to access a certain column of data in SDRAM. CAS latency, or simply CAS, is known as Column Address Strobe time, sometimes referred to as tCL.
tRCD (RAS to CAS Delay)
The number of clock cycles needed between a row address strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. tRCD stands for Row address to Column address Delay time.
tRP (RAS Precharge)
The number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. It stands for Row Precharge time.
tRAS (Row Active Time)
The minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. It's known as active to precharge delay. According to Mushkin, in practice for DDR SDRAM, this should be set to at least tRCD + tCAS + 2 to allow enough time for data to be streamed out.
Do remember that SDRAM is idle, and does not remain fixed in the banks. The controller has write it over and over again really quick, to able to retain it, so the CPU can use it. Its like an excel grid (rows/columns), which get filled left to right, top to bottom.
