vickybat
I am the night...I am...
Intel is finally going to launch its first HPC ( High performance computing) co-processor codenamed knights corner and comercially, the Xeon-Phi.
This is straightaway being implemented in two of world's finest supercomputers i.e TACC Stampede and Cray's XC30.
Cray currently has the world's fastest supercomputer named Titan at Oak Ridge National Laboratory which uses 18600 bulldozer opterons and 18600 GK110 based Nvidia K20X tesla gpu's.
But intel has a taken a very different approach here than what conventional gpu manufacturers like nvidia and amd has taken using an independent code platform like cuda and open-cl to tap out maximum performance from their architectures. They have taken the x86 instruction approach which enables developers to build compute apps using existing languages like c, c++ and FORTRAN.
Developing for intel's new co-processor platform won't require any development kits consisting of expensive Xeon-Phi's but a developer can build an app for a core i3 3220 and optimize it for parallelism in order to take maximum advantage of Xeon-phi. So developing costs will be massively less and easy because coding in cuda and open-cl is tedious.
Intel here employs its MIC (Many core architecture) comprising of 66 fully functional x86 cores with a 512 bit SIMD vector processing unit all attached in a ring bus to fully utilize cache and other resources efficiently. This is fabricated using 22nm 3d trigate transistors seen in ivybridge. Being pci-express compliant, they have ample bandwidth at disposal.
This is actually based on intel's previous larabee microarchitecture which was scraped as it wasn't competitive then. But its proving itself highly competitive in HPC environment.
Read the link below for a more detailed explanation.
Xeon Phi: Intel's Larrabee-Derived Card In TACC's Supercomputer : Introducing Intel Xeon Phi
This is straightaway being implemented in two of world's finest supercomputers i.e TACC Stampede and Cray's XC30.
Cray currently has the world's fastest supercomputer named Titan at Oak Ridge National Laboratory which uses 18600 bulldozer opterons and 18600 GK110 based Nvidia K20X tesla gpu's.
But intel has a taken a very different approach here than what conventional gpu manufacturers like nvidia and amd has taken using an independent code platform like cuda and open-cl to tap out maximum performance from their architectures. They have taken the x86 instruction approach which enables developers to build compute apps using existing languages like c, c++ and FORTRAN.
Developing for intel's new co-processor platform won't require any development kits consisting of expensive Xeon-Phi's but a developer can build an app for a core i3 3220 and optimize it for parallelism in order to take maximum advantage of Xeon-phi. So developing costs will be massively less and easy because coding in cuda and open-cl is tedious.
Intel here employs its MIC (Many core architecture) comprising of 66 fully functional x86 cores with a 512 bit SIMD vector processing unit all attached in a ring bus to fully utilize cache and other resources efficiently. This is fabricated using 22nm 3d trigate transistors seen in ivybridge. Being pci-express compliant, they have ample bandwidth at disposal.
This is actually based on intel's previous larabee microarchitecture which was scraped as it wasn't competitive then. But its proving itself highly competitive in HPC environment.
Read the link below for a more detailed explanation.
Xeon Phi: Intel's Larrabee-Derived Card In TACC's Supercomputer : Introducing Intel Xeon Phi
