MSI Calls Bluff on Gigabyte's PCIe Gen 3 Ready Claim

Jaskanwar Singh

Jaskanwar Singh

Aspiring Novelist
MSI Calls Bluff on Gigabyte's PCIe Gen 3 Ready Claim | techPowerUp

In August, Gigabyte made a claim that baffled at least MSI, that scores of its motherboards are Ready for Native PCIe Gen. 3. Along with the likes of ASRock, MSI was one of the first with motherboards featuring PCI-Express 3.0 slots, the company took the pains to educate buyers what PCI-E 3.0 is, and how to spot a motherboard that features it. MSI thinks that Gigabyte made a factual blunder bordering misinformation by claiming that as many as 40 of its motherboards are "Ready for Native PCIe Gen. 3." MSI decided to put its engineering and PR team to build a technically-sound presentation rebutting Gigabyte's claims.

MSI begins by explaining that PCIe support isn't as easy as laying a wire between the CPU and the slot. It needs specifications-compliant lane switches and electrical components, and that you can't count on certain Gigabytes for future-proofing.


MSI claims that apart from the G1.Sniper 2, none of Gigabyte's so-called "Ready for Native PCIe Gen. 3" motherboards are what the badge claims to be, and that the badge is extremely misleading to buyers. Time to refill the popcorn bowl.
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sumonpathak

sumonpathak

knocking on heavens door
^^^they should be angry:p

if my understanding are right then pcie 2.0 to pcie 3.0 should be possible by an machine language update[read BIOS update]

PCI-Express 3.0 explained | bit-tech.net
Typically PCI-Express (and a whole lot of other signalling buses) use an '8b/10b' encoding, which means ten bits are transferred for eight bits (one byte) of actual data. That 20 per cent overhead is considerable, and as we've seen from CPUs, frequencies cannot perpetually increase. This means that this overhead becomes ever more an issue as the bandwith increases.

To work around this problem, PCI-Express 3.0 encodes the data in a much larger '128b/130b' chunk, and then 'a known polynomial is applied to a data stream in a feedback topology', with an 'inverse polynomial' sat at the other end to decode the data. In more human terms, this is basically a hard-coded mathematical function that is designed to evenly spread the 0s and 1s (which are electrical clock blips), so they don't interfere with each other during transport. This technique is called 'scrambling'.
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