PCI-SIG, the entity that defines the bandwidth, form factor and other specifications of the all popular PCI Express Bus (PCIe) announced at the Hot Chips 2017 conference that the PCIe 4.0 standard will arrive later in 2017. Additionally, PCI-SIG is going to speed up the development and feedback process for PCIe 5.0 so that the final standard can be ratified by 2019.
The Evolution of the PCIe Standard
The PCIe standard has a cadence cycle of roughly four years. The first ever PCI standard was unveiled in 1992, and it was a fairly fast bus with a frequency of 33 MHz netting a bandwidth of 133 MB/s. PCI 2.0 came a year later with twice the frequency but with 4x the bandwidth. The next revision was PCI-X in 1999, then came PCI-X 2.0 in 2002 along with the first ever PCIe 1.x standard as well. The jump from PCI-X 2.0 to PCIe 1.x brought with it a tremendous leap in frequency as it moved to 2.5 GHz and had a bandwidth of 8 GB/s. It was followed by PCIe 2.x in 2006 and PCIe 3.x in 2010. Both maintaining a gap of four years. PCIe 4.0, that arrives later this year will have a frequency of 16 GHz and a bandwidth of 64 GB/s. And PCIe 5.0 doubles that to 32 GHz for the frequency and 128 GB/s for the bandwidth.
The PCIe 4.0 standard is currently undergoing development and as it stands right now, we’re looking at the revision 0.9. The final specification will be ratified at revision 1.0. However, silicon manufacturers have already jumped the gun and started producing PHYs that support what could be revision 1.0.
The need for PCIe 4.0
The PCIe standard has been the interconnect of choice for decades now. It has been widely adopted by all major vendors in the silicon manufacturing industry and future interface designs are mostly based on the PCIe standard as the interconnect. We see PCIe is used for add-in cards on PCs and even mobile devices, networking cards, proprietary interfaces, etc.
The introduction of the PCIe 3.0 standard was deemed a little too early since the most bandwidth intensive hardware of 2010 could hardly saturate the PCIe 2.0 interface let alone PCIe 3.0. Essentially, PCIe 4.0 was not needed at all till now.
However, over the last couple of years, we’ve seen a huge leap in technological progress along the lines of GPUs, networking and storage protocols. Both NVIDIA and AMD have their own lineup of compute specific GPUs which are used for AI, VR, animation, post-production, editing, etc. NVIDIA has the Tesla lineup and AMD has the FirePro and Radeon Vega Frontier for these purposes. On the storage front, we have moved on from the humble SATA-III interface to the NGFF or M.2 interface to make use of PCIe lanes for the extra bandwidth. Gone are the days when a mechanical hard drive’s 133 MB/s top speed was enough for anyone owning a PC, an SSD is a bare minimum and if you make that an NVMe SSD, then you’re talking. On the networking side, 5G has suddenly sprung up and gained a lot of traction. Closer to home, we have adopted 4G across the nation in record time thanks to Reliance Jio. All of these monumental technologies also consume a monumental amount of data. And these have started hitting PCIe 3.0’s throughput ceiling.
It has now come to a state where the PCIe standard has started to become a bottleneck that impedes technological progress. Hence, we need the PCIe 4.0 standard to be ratified at the earliest.
Vendors are already shipping PCIe 4.0 devices
If there is a need, then there will be a product to satisfy that need. Silicon vendors aren’t going to wait for long for PCI-SIG to get on with their certification process. And given how the PCIe standard functions, it isn’t that difficult to scale PCIe 3.0 to meet the higher bandwidth needs of the industry. Which is why we already have vendors such as XILINX, PLDA, GUC, Synopsys and Cadence offer controllers with 16 GT/s line speeds. These controllers are then used by hardware manufacturers to introduce PCIe 4.0 (draft) into their offerings.
And that’s just PCIe 4.0, we even have devices rated for 28 GHz and 56 GHz in the industry which is hitting (28 GHz) PCIe 5.0 or has crossed (56 GHz) it. As of now, PCIe 5.0 is in the early stages and the current specifications are detailed in version 0.3 of the standard.